1. Field of the Invention
This invention relates to integrated circuit (IC) memory technology, and more particularly, to a sense amplifier for a high-speed IC memory device, which can help reduce the sensing latency during read operations to the memory device so as to allow fast access to the memory device.
2. Description of Related Art
The performance of a computer system is dependent on CPU speed as well as memory access speed. Therefore, the computer performance can be enhanced by increasing the memory access speed. At present, DRAM (Dynamic Random-Access Memory) is widely used as the primary memory in computer systems due to its high access speed. Newer types of DRAMs, such as FPM (Fast Page Mode) DRAM, EDO (Extended Data Out) DRAM, and SDRAM (Synchronized DRAM), can provide very high access speed.
It is well known that a DRAM device is typically coupled with a sense amplifier to its bit lines, which is used to amplify the differential data signal on the bit lines to an adequate level that can be detected by the memory interface coupled to the DRAM device.
The most widely used type of sense amplifier is the so-called latch-type sense amplifier. One drawback to this type of sense amplifier, however, is that its operation requires large sensing latency and large levels of differential data signal on the bit lines. Therefore, the latch-type sense amplifier is not suitable for use with a high-speed memory device.
FIG. 1 is a schematic diagram showing the circuit structure of a conventional sense amplifier.
As shown, the sense amplifier 10 is connected to a pair of complementary bit lines BL, BLB of a memory cell 1 10 of a memory device 100, and a pair of complementary data lines DL, DLB, and is composed of a pair of NMOS transistors 12, 14, and a pair of PMOS transistors 16, 18.
The circuit diagram of the sense amplifier 10 includes four nodes A, B, C, D, wherein the node A is connected via a third NMOS transistor 26 to the ground GND, the node B is connected to the bit line BL, the node C is connected to the bit line BLB, and the node D is connected via a third PMOS transistor 24 to the system voltage VCC.
The first NMOS transistor 12 is connected in such a manner that its drain is connected to the node A, its source is connected to the node B, and its gate is connected to the node C. The second NMOS transistor 14 is connected in such a manner that its drain is connected to the node A, its source is connected to the source of the second PMOS transistor 18, and its gate is connected to the node B. The first PMOS transistor 16 is connected in such a manner that its source is connected to the node B, its drain is connected to the node D, and its gate is connected to the node C. The second PMOS transistor 18 is connected in such a manner that its source is connected to the source of the second NMOS transistor 14, it drain is connected to the node D, and its gate is connected to the node B.
The sense amplifier 10 is used to amplify the differential data signal on the BL and BLB bit lines to a detectable level so that the data signals can be detected by the memory interface (not shown) connected to the data lines DL, DLB which are connected respectively via two NMOS transistors 20, 22 to the BL and BLB bit lines. A column select signal COL is used to control the ON/OFF states of these two NMOS transistors 20, 22.
Furthermore, the ON/OFF states of the third PMOS transistor 24 and the third NMOS transistor 26 are respectively controlled by a PSA (Positive Sense Active) signal and an NSA (Negative Sense Active) signal in such a manner that when the third PMOS transistor 24 is switched on by the PSA signal, it causes the node D to take on the system voltage VCC, and when the third NMOS transistor 26 is switched on by the NSA signal, it causes the node A to take on the ground voltage. The logic states of the PSA signal and the NSA signal are complementary to each other; i.e., when the NSA is at low-voltage logic state, the PSA signal is at high-voltage logic state, and vice versa. Furthermore, an NMOS transistor 28 is connected from the bit line BL to the bit line BLB, with its gate being connected to an equalizing signal EQ. When the equalizing signal EQ switches on the NMOS transistor 48, it causes the bit line BL and the bit line BLB to be equalized in voltage state.
One drawback to the forgoing sense amplifier of FIG. 1, however, is that the differential data signal on the BL and BLB bit lines should be relative large so that they can be detected by the sense amplifier, which would undesirably result in a large sensing latency that slows the access speed to the memory. This drawback makes the sense amplifier unsuitable for use with high-speed IC memory device.